The present invention relates generally to circuit analysis, and more specifically relates to generating images of circuits via dual-mode magnetic field induction for defect analysis.
The testing and analysis of circuits, printed circuit boards (PCBs) and the like is a complex and a costly step in the manufacture of these devices. Moreover, the complexity and the cost of circuit test and analysis continues to rise as circuits and PCBs are continually made smaller. As used hereinafter, the term “circuit” refers to circuits, PCBs, PCBs having attached circuits and the like unless otherwise indicated. The rise in the complexity and the cost of testing and analysis of circuits is attributable, in part, to the tester interfaces used to contact circuits for passing electrical test signals to the circuits and receiving response signals therefrom. Traditional tester interfaces include bed of nails interfaces, sockets, probe cards and the like. As the pitch of circuit interface contacts (e.g., contact pads, bonding pads, solder balls, solder mounds, leads, and the like) enter the sub-millimeter range, the micron range, and the sub-micron range, the pitch of adjacent tester contacts on tester interfaces similarly enter these ranges. The costs associated with the manufacture of such tester interfaces and the maintenance fees therefore, rise to relatively high levels yielding testing and analysis of circuits relatively costly.
Testing and analysis of circuits are costly due not only to the relatively high cost for development, manufacture, and maintenance of tester interfaces, but also because for each unique circuit, a unique tester interface is typically manufactured for the circuit. Moreover, unique test programs are typically generated to drive each unique circuit and its associated tester interface. Test program development typically takes a few days to several months and even a year or more for relatively complex circuits.
Further, contact testing of circuits often fails to expose flaws that lead to relatively early failure (often referred to as infant mortality) of circuits. For example, contact testing is often of limited use for detecting flaws in metal lines (e.g., cracks, voids, etc.) and circuit elements (e.g., transistors, inductors, resistors, etc.) that are operational, but that have defects that may lead to uneven heating and the like, which in turn often leads to relatively high infant mortality. Flaws that lead to high infant mortality are often detected through destructive techniques that ultimately render devices unsuitable for their intended use.
Therefore, new apparatus and methods are needed that provide for limited physical contact with circuits under test, have a relatively low dedication to specific circuits, and that are configured to non-destructively detect internal flaws that may not be detected via contact testing techniques.